1. Field of the Invention
The invention relates generally to a device and method of determining the amount and location of decoupling capacitance or enhanced local wiring to be added during the design and layout of a semiconductor circuit to optimally reduce dynamic supply voltage fluctuations during circuit operation.
2. Description of the Related Art
As the design and layout of semiconductor circuits, or microcircuits, or chips, become more complex, and in particular, as there is an increase in complexity of very large scale integration (VLSI) layout, an increase in operational frequency and the use of supply voltage scaling, there is an ever increasing need to remove or reduce undesired noise from the chip design. A chip's power distribution network is a major noise source as the fluctuations in supply voltage due to the parasitic resistance, inductance and capacitance in the network alter signals' voltage levels and can cause malfunctioning of the chip's circuits. Designing a robust power distribution network for low dynamic voltage fluctuations has become a challenging task. Extremely dense and complex circuit layouts for high frequency operation necessitate reduction of these undesired noise levels, especially at some sensitive parts of circuits such as clock generators and analog circuits. In general, it is important to improve the voltage fluctuations of all critical voltage violation regions (known as “hot spot regions”) of a semiconductor circuit layout.
Static voltage drop (known as “IR drop”) is usually addressed through increased metallization (reduction of resistance), pad placement, topology optimization and power-density-aware “floor planning.” For limiting dynamic voltage fluctuations in a power network, the chief technique is to place one or more decoupling capacitors (known also as “decaps” in an abbreviated manner) close to a voltage violation hot spot region. This requires that there be sufficient white space, i.e., clear area on the chip, near the hot spot region. Sometimes circuit density does not allow sufficient white space to effectively add decaps near a hot spot region. Additionally, decaps alone are effective in suppressing noise only if placed very close to the noise sources.
For example, when a large gate such as a clock driver creates a sudden and high current demand, charge stored in a decap should be transported very quickly to that gate in order to reduce the supply voltage droop. If the path between the decap and the high current demand gate has significant resistance, then the charge transportation cannot occur as fast as required. This diminishes the effectiveness of the decap and requires more decap to be added. However, the decoupling capacitance density achievable may be limited by the process technology and by the limited amount of white space available around a problem spot. Because of this, it is not always possible to place the entire amount of required decap close enough to a hot spot region to achieve effective dynamic noise reduction.
As understood in the art, decap budgeting and placement is a non-linear optimization problem. Several known solution methods make very simple calculations for decap, resulting in overestimation. Other methods use non-linear optimization techniques involving some metric of dynamic supply noise. In another method, sensitivities of a noise metric to added decaps (which are known as adjoint sensitivities) are computed by simulating the original network and a derived network (known as the adjoint network) and then combining the waveforms from these two simulations in a mathematical process called convolution. The adjoint sensitivities are then used in a non-linear optimization using a quadratic solver.
In another proposed method in the art, the conjugate gradient (CG) method is used for optimization, wherein the gradients are computed using simplified adjoint sensitivity calculations. In another method, the known technique of divide-and-conquer is used to reduce the size of the sensitivity-based optimization. A further known method solves the nonlinear optimization through a sequence of linear programming methods. These methods are not practical for very large chip designs as the computation of adjoint sensitivities, or gradients, and the non-linear optimization are both very expensive in runtime and memory resources. In another method known in the art, the problem size is reduced using the geometric multigrid concept and then a sequential quadratic program method is used to optimize the reduced grid. Due to the use of geometric multigrid, this method works well only for very uniform power grid topologies.
Further complicating the problem, these techniques add decap and recompute sensitivity in an iterative procedure. As the complexity of one adjoint sensitivity computation is the same as one transient analysis, the iterative nonlinear optimization procedure becomes quite expensive and time consuming. In addition, the adjoint sensitivity calculation typically needs to store waveforms at every node in both the original and the adjoint networks, which may exhaust the memory resource for large networks.
Several charge-based decap estimation techniques have also been proposed in the art in the context of power supply noise-aware floor planning. An approximate lumped decoupling capacitance is estimated for each floor plan module, with an assumption that the original voltage of decoupling capacitance is a perfect VDD voltage reference; however, the parasitic capacitance and existing decap value are not considered in these methods, which causes inaccuracies.
Because of limitations of these known solution methods, there is a need for an improved method or process of decap optimization.
In the following detailed description of exemplary embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific exemplary embodiments in which the invention may be practiced.